DE1-SoC-MTL2 Development Kit
The all-in-one embedded solution offered on the DE1-SoC-MTL2, in combination of a LCD touch panel and digital image module, provides embedded developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of FPGA-based embedded processing system such as mitigating design risk and obsolescence, design reuse, lowering bill of material (BOM) costs by integrating powerful graphics engines within the FPGA.
For SoC reference designin Linux for touch-screen display, please refer to the “Programming Guide for Touch-Screen Display” document in the System CD of DE1-SoC-MTL2.
■Features
●Dual-core ARM Cortex-A9 (HPS)
●85K programmable logic elements
●4,450 Kbits embedded memory
●6 fractional PLLs
●2 hard memory controllers
●Quad serial configuration device –EPCS128 for the FPGA
●On-board USB Blaster II (normal type B USB connector)
●64MB (32Mx16) SDRAM for the FPGA
●1GB (2x256MBx16) DDR3 SDRAM for the HPS
●microSD card socket for the HPS
●Two port USB 2.0 Host (ULPI interface with USB type Aconnector)
●UART to USB(USB Mini B connector)
●10/100/1000 Ethernet
●PS/2 mouse/keyboard
●IR emitter/receiver
●I2C multiplexer
●Two 40-pin expansion headers
●One 10-pin ADC input header
●One LTC connector(one Serial Peripheral Interface (SPI) master ,one I2C bus,and one GPIO interface)
●24-bit VGA DAC
●24-bit CODEC, line-in, line-out, and microphone-in jacks
●TV decoder (NTSC/PAL/SECAM) and Video-in connector
●Fast throughput rate: 1 MSPS
●Channel number: 8
●Resolution: 12-bit
●Analog input range: 0 ~ 2.5 V or 0 ~ 5V by selecting the RANGE bit in the control register
●5 user keys(4 for the FPGA and 1 for the HPS)
●10 user switches for the FPGA
●11 user LEDs(10 for the FPGA and 1 for the HPS)
●2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n)
●Six 7-segment displays
●G-sensor for the HPS
●12V DC input
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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12/18/2014 |
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V1.0 |
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2.6 MB |
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