Silicon Labs(芯科科技) C8051F120/1/2/3/4/5/6/7,C8051F130/1/2/3 MCU数据手册

2023-08-31

The C8051F12x and C8051F13x device families are fully integrated mixed-signal System-on-a-Chip MCUs with 64 digital I/O pins (100-pin TQFP) or 32 digital I/O pins (64-pin TQFP).
Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection.
With on-chip VDDmonitor, Watchdog Timer, and clock oscillator, the C8051F12x and C8051F13x devices are truly stand-alone System-on-a-Chip solutions. All analog and digital peripherals are enabled/disabled and configured by user firmware. The Flash memory can be reprogrammed even in-circuit, providing nonvolatile data storage, and also allowing field upgrades of the 8051 firmware.
On-board JTAG debug circuitry allows non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production MCU installed in the final application. This debug system supports inspection and modification of memory and registers, setting breakpoints, watchpoints, single stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging using JTAG.
Each MCU is specified for operation over the industrial temperature range (-45 to +85 °C). The Port I/O, RST, and JTAG pins are tolerant for input signals up to 5 V. The devices are available in 100-pin TQFP or 64-pin TQFP packaging. Table 1.1 lists the specific device features and package offerings for each part number. Figure 1.1 through Figure 1.6 show functional block diagrams for each device.

Silicon Labs

C8051F133-GQC8051F133-GQRC8051F133C8051F13xC8051F12xC8051F127-GQRC8051F127-GQC8051F127C8051F125-GQC8051F125C8051F125-GQRC8051F124-GQRC8051F124-GQC8051F124C8051F131-GQC8051F131C8051F130-GQRC8051F130C8051F130-GQC8051F122C8051F122-GQC8051F121C8051F121-GQRC8051F121-GQC8051F132-GQC8051F132C8051F132-GQRC8051F126-GQC8051F126-GQRC8051F126C8051F123C8051F123-GQC8051F123-GQRC8051F120-GQC8051F120C8051F120-GQR

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微控制器微处理器Mixed Signal ISP Flash MCU

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通信设备 ]工业电子 ]汽车电子 ]消费电子 ]

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Datasheet

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2005年12月01日

Preliminary Rev. 1.4 12/05

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