Leading-Edge Memory Solutions for UltraScale & UltraScale+ FPGA

PublishTime：2022-03-23

●GSI Technology customers now have access to a free Controller IP for our SigmaQuad-II+™ and SigmaDDR-II+™ SRAMs, for use with Xilinx UltraScale™ and UltraScale+™ FPGAs.
●GSI’s SRAM Port IP supports both Burst of 2 (B2) and Burst of 4 (B4) versions of these devices, as well as x18 and x36 data widths.
●Controller IP Overview
■Utilizes a “2:1 Mux” configuration for max performance: SRAM clock = 2x FPGA User Interface clock
■Read Latency = ~15 FPGA User Interface clock cycles (2:1 Mux)
■Validated by GSI on a KU040 evaluation board
■Verified by multiple customers with various FPGAs from the UltraScale family

Brand of Product：	GSI Technology
Part#：	GS82582Qxx 、 GS81302QxxA 、 GS8342QxxB 、 GS8662QxxB 、 GS82582Dxx 、 GS81302DxxA 、 GS8662DxxB 、 GS8342DxxB 、 GS8182DxxB 、 GS82582Txx 、 GS81302TxxA 、 GS8662TxxB 、 GS8342TxxB 、 GS8182TxxB 、 KU040 More Part#
Product Category：	SigmaQuad-II+ SRAMs 、 SigmaDDR-II+ SRAMs 、 UltraScale FPGAs 、 UltraScale+ FPGAs More
Application：	More
Data Type：	Supplier and Product Introduction More
Safety & Environment Standards：	More
Operating Temperature：	Please see the document for details
Qualification Grade：	More
Qualification Approval：	More
Package：
Language：	English Chinese Chinese and English Japanese
Date of Creation：	2018/2/13
Version Number：
Data Encoding：
Data Size：	1.7 MB

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