Lattice Diamond 3.12 Tutorial
●This tutorial leads you through all the basic steps of designing and implementing a mixed VHDL and Verilog design targeted to the MachXO3L device family. It shows you how to use several processes, tools, and reports from the Lattice Diamond™ software to import sources, run design analysis, view design hierarchy, and inspect strategy settings. The tutorial then proceeds to step through the processes of examining the device resources, setting timing and location assignments, programming the device, and adding a logic analyzer to the design.
■About the Tutorial：
▲When you have completed this tutorial, you should be able to do the following:
●Create a new Lattice Diamond project.
●Create an IPexpress module.
●Verify functionality with simulation.
●Inspect strategy settings.
●Examine resources.
●Set timing and location assignments.
●Process the design.
●Examine static timing analysis results.
●Analyze power consumption.
●Run export utility programs.
●Download a bitstream to an FPGA.
●Use Reveal Inserter to add on-chip debug logic.
●Use Reveal Logic Analyzer to perform logic analysis.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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August 16, 2021 |
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version 3.12 |
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1.1 MB |
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