AES128 IP Core Product Specification
■ Support AES ECB mode standard.
■ Support 128-bit key size.
■ Support input data width128-bit.
■ Throughput rate at 11.6 Mbits/MHz.
■ Speed up to 2.9 Gbps @250MHz.
■ 128-bit data calculation time is constant at 11 clock cycles.
● General Description:
■ AES128 IP Core (AES128IP) implement the advanced encryption standard (AES) algorithm which is widely used in many applications like file encryption, processor security, and secure file transfer protocol.
■ AES is a symmetric block cipher algorithm of the Rijndael family. Please find more details in the Federal Information Processing Standards Publication (FIPS PUB) 197.
■ AES128IP is consisted of AES128ENC module, that is encryption module and AES128DEC module, that is decryption module as shown in Figure 1.
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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September 10, 2021 |
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Rev1.01 |
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433 KB |
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