Si53320-28 Low-Jitter LVPECL Fanout Clock Buffers Data Sheet
●The Si53320–28 family is available in multiple configurations, with some versions offer-ing a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance.
■KEY FEATURES
●Ultra-low additive jitter: 50 fs rms
●Built-in LDOs for high PSRR performance
●Up to 10 LVPECL Outputs
●Any-format Inputs (LVPECL, Low-powerLVPECL, LVDS, CML, HCSL, LVCMOS)
●Wide frequency range: dc to 1250 MHz
●Output Enable option
●Multiple configuration options
▲Dual Bank option
▲2:1 Input Mux operation
●RoHS compliant, Pb-free
●Temperature range: –40 to +85 °C
Si53323 、 Si53320 、 Si53327 、 Si53328 、 Si53321 、 Si53326 、 Si53322 、 Si53325 、 Si53320-B-GT 、 Si53321-B-GM 、 Si53321-B-GQ 、 Si53322-B-GM 、 Si53323-B-GM 、 Si53325-B-GM 、 Si53325-B-GQ 、 Si53326-B-GM 、 Si53327-B-GM 、 Si53328-B-GM |
|
|
|
Datasheet |
|
|
|
Please see the document for details |
|
|
|
|
|
20-TSSOP;32-QFN;32-eLQFP;16-QFN;24-QFN |
|
English Chinese Chinese and English Japanese |
|
December 3, 2021 |
|
Rev. 1.2 |
|
|
|
3.4 MB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.