Si53320-28 Low-Jitter LVPECL Fanout Clock Buffers with up to 10 LVPECLOutputs from Any-Format Input and Wide Frequency Range fromDC up to 1250 MHz
●The Si53320–28 family is available in multiple configurations, with some versions offering a selectable input clock using a 2:1 input mux. Other features include independent output enable and built-in format translation. These buffers can be paired with the Si534x clocks and Si5xx oscillators to deliver end-to-end clock tree performance
●KEY FEATURES
■Ultra-low additive jitter: 50 fs rms
■Built-in LDOs for high PSRR performance
■Up to 10 LVPECL Outputs
■Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS)
■Wide frequency range: dc to 1250 MHz
■Output Enable option
■Multiple configuration options
■Dual Bank option
■2:1 Input Mux operation
■RoHS compliant, Pb-free
■Temperature range: –40 to +85 °C
Si53320-28 、 Si5xx 、 Si534x 、 Si53323 、 Si53320 、 Si53327 、 Si53328 、 Si53321 、 Si53326 、 Si53325 、 Si53322 、 Si53320-B-GT 、 Si53321-B-GM 、 Si53321-B-GQ 、 Si53322-B-GM 、 Si53323-B-GM 、 Si53325-B-GM 、 Si53325-B-GQ 、 Si53326-B-GM 、 Si53327-B-GM 、 Si53328-B-GM |
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Datasheet |
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Please see the document for details |
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20-TSSOP;16-QFN;32-QFN;32-eLQFP;24-QFN |
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English Chinese Chinese and English Japanese |
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July 26, 20212 |
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Rev. 1.2 |
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3.4 MB |
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