PCIe X1 IP Core -Lattice Radiant Software User Guide
■PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multi-drop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus.
■The Lattice PCIe X1 Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express® Bus. The Lattice PCIe X1 Core implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks from third party vendors (Analog Bits Inc., and Northwest Logic Inc.).Throughout this document, the Link Layer block refers to the entire logical block that consists of three sub layers namely, PHY logical layer (that is, LTSSM, PIPE, and other related function), Data Link Layer, and Transaction Layer. The PHY block refers to the PMA and PCS.
■The Lattice PCIe X1IP Core is supported in CrossLink™-NX and Certus™-NX FPGA device families and is available in Lattice Radiant™ Software.
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PCI-EXP1-CNX-U 、 PCI-EXP1-CNX-UT 、 PCI-EXP1-CTNX-U 、 PCI-EXP1-CTNX-UT 、 CrossLink-NX 、 Certus-NX 、 LIFCL-40 、 LFD2NX-40 |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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December 2020 |
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Revision 1.3 |
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FPGA-IPUG-02091-1.3 |
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3.1 MB |
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