SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge Soft IP User Guide
■Many Image Signal Processors (ISP) or Application Processors (AP) use the Mobile Industry Processor Interface(MIPI®) Camera Serial Interface 2(CSI-2) standard for image sensor inputs. However, some high resolution CMOS image sensors use a proprietary SubLVDS output format. The Lattice Semiconductor SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge IP for Lattice Semiconductor CrossLink™ solves the interface mismatch between subLVDS output image sensor and an ISP/AP using MIPI CSI-2 interface.
■This user guide is for SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge Soft IP design version 1.x.
●Features
■The key features of the SubLVDS to MIPI CSI-2 Image Sensor Interface Bridge IP are:
▲Supports four, six, eight or ten data lanes from an image sensor in 10-bit (RAW10) or 12-bit (RAW12) pixel widths
▲Generates XVS and XHS for image sensors in slave mode
▲Interfaces to MIPI CSI-2 Receiving Devices with four data lanes up to 6 Gb/s total bandwidth.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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April 2019 |
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Revision 1.4;IP Version 1.2 |
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FPGA-IPUG-02006-1.4 |
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2 MB |
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