Memory Modules User Guide
■This technical note discusses memory usage for the FPGA devices supported by Lattice Radiant Software. It is intended to be used by design engineers as a guide to integrating the EBR (Embedded Block Random Access Memory)based memories for all device families in Lattice Radiant Software.
■Behavioral code for Single-Port RAM and Pseudo Dual-Port RAM are supported. Synthesis tool is expected to infer sysMEM™ EBR.
■Designers can utilize the memory primitives using two different methods described below.
▲Using Module/IP Block Wizard–The Module/IP Block Wizard user interface allows you to specify the required memory type and size. Module/IP Block Wizard takes this specification and instantiates a synthesizable RTL (register transfer level)code and sets the appropriate parameters based on the user interface setting.
▲Using PMI (Parameterized Module Instantiation)–PMI allows experienced users to skip the graphical user interface and utilize the configurable memory primitives on-the-fly from the Lattice Radiant Software project navigator. The parameters and the control signals needed in Verilog are set by the user. The top-level design has the instantiation of a synthesizable RTL code,which is inferred during synthesis.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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January 2019 |
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Version 1.1 |
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FPGA-IPUG-02033 |
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1.8 MB |
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