SBN1661G_M18, SBN1661G_M02, SBN0080G_S18, SBN0080G S02 Dot-matrix STN LCD Driver with 32-row x 80-column Display Data Memory
■the SBN1661G_M18,
■the SBN1661G_M02,
■the SBN0080G_S18, and
■the SBN0080G_S02.
●Both the SBN1661G_M18 and the SBN1661G_M02 can drive 16 COMMONs and 61 SEGMENTs and can be used as master in a master-slave connection. They both have 32-row x 80-column Display Data Memory. Functionally, their only difference is that the SBN1661G_M18 has an on-chip RC-type oscillator and can provide clock to slave, while the SBN1661G_M02 does not have an on-chip oscillator and needs external clock source.
●Both the SBN0080G_S18 and the SBN0080G_S02 are purely SEGMENT drivers. They do not have COMMON outputs and are used for segment expansion in a master-slave connection. Both devices need either a master or an external clock source to provide clock. The only difference between these two chips is their operating frequency. The SBN0080G_S18’s operating frequency is 18 KHz, while the SBN0080G_S02’s operating frequency is 2KHz
●All four devices have on-chip Display Data Memory of 32-rows x 80-columns, for storing display data. Dot-matrix mapping method is used to drive the LCD panel. Therefore, a bit of the Display Data Memory corresponds to a pixel on the LCD panel. SEGMENT drivers provide display data to the LCD panel and COMMON drivers provide row-scanning signal.
●All four devices have a set of internal registers. These internal registers must be properly programmed to ensure proper operation of the devices.
●Display on the LCD panel is controlled by a host microcontroller. All four devices communicate with the host microcontroller via data bus and control bus. The data bus is 8-bit wide. The control bus are READ, WRITE, and ChipSelect. The host microcontroller can perform READ/WRITE operations to the internal registers and Display Data RAM of all four devices. A wide variety of microcontrollers can easily interface with the devices, as the devices can accept both 80-type interface timing and 68-type interface timing. The selection of interface timing is via the dual-function RESET/IF pin.
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SBN1661G_M18 、 SBN1661G_M02 、 SBN0080G_S18 、 The SBN1661G_X 、 SBN1661G_M18-LQFPG 、 SBN1661G_M18-QFPG 、 SBN1661G_M18-LQFP 、 SBN1661G_M18-QFP 、 SBN1661G_M18-D 、 SBN1661G_M02-LQFPG 、 SBN1661G_M02-QFPG 、 SBN1661G_M02-LQFP 、 SBN1661G_M02-QFP 、 SBN1661G_M02-D 、 SBN0080G_S18-LQFPG 、 SBN0080G_S18-QFPG 、 SBN0080G_S18-LQFP 、 SBN0080G_S18-QFP 、 SBN0080G_S18-D 、 SBN0080G_S02-LQFPG 、 SBN0080G_S02-QFPG 、 SBN0080G_S02-LQFP 、 SBN0080G_S02-QFP 、 SBN0080G_S02-D 、 SBN0080G_S02 |
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Datasheet |
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Please see the document for details |
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QFP100;LQFP100 |
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English Chinese Chinese and English Japanese |
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2007/7/5 |
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V6.5A |
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1003 KB |
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