ADSP-2156x SHARC+ Processor Hardware Reference
●The ADSP-2156x SHARC+ Processor Hardware Reference provides architectural information about the ADSP-2156x processors. This hardware reference provides the main architectural information about these processors. The architectural descriptions cover functional blocks, buses, and ports, including all features and processes that they support.
■Intended Audience
●The primary audience for this manual is a programmer who is familiar with Analog Devices processors. The manual assumes the audience has a working knowledge of the appropriate processor architecture and instruction set. Pro-grammers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts, such as programming reference books and data sheets, that describe their target architecture.
■What's New in This Manual
●This manual is revision 1.0 of the ADSP-2156x SHARC+ Processor Hardware Reference. The following changes are included in this edition:
●Added Introduction, HADC, and TMU chapters
●Updated the Oscillator Watchdog section of the CGU chapter
●Updated the Programming the DMC Controller section of the DMC chapter
●Updated the OTP Layout section of the OTPC chapter
●Updated the Internal Timer Connections information in the GP Timer chapter
●Updated the Boot ROM and Booting the Processor chapter
●Updated Digital Filter Group Delay section of the ASRC chapter
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ADSP-2156x 、 82-100137-01 、 ADSP-BF7xx 、 ADSP-BF6xx 、 ADSP-BF5xx 、 ADSP-21xxx 、 ADSP-SC5xx 、 ADSP-215xx |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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December 2020 |
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Revision 1.0 |
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11.4 MB |
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