STM32H745/755 and STM32H747/757 lines inter-processor communications Application note
■ High performance STM32 microcontrollers and release constraints on software architecture open the door to more advanced software solutions. Advanced software applications require independent components to run simultaneously. Microcontrollers of the STM32H745/755 and STM32H747/757 lines feature an asymmetric dual-core architecture; thus, processing parallelism is guaranteed with two CPUs capable of running different payloads. Nevertheless, there are often tasks that need to communicate with one another to share information and ensure correct processing. For these reasons, the inter-processor communication (IPC) layers are needed to link data dependent tasks.
■ To ease core-to-core interactions and reduce time to market, STM32CubeH7 propose a set of standard middleware that implement the inter-processor communication channel (IPCC) between the Arm® Cortex®-M7 and Arm®Cortex®-M4. This application note provides an overview of the dual-core communication technique. It introduces the inter-processor communication channels such as OpenAMP, RPMsg, FreeRTOS™ as well as the message buffer and custom communication mechanism. It also provides a detailed flowchart with snippet code example to describe how to use OpenAMP and FreeRTOS™ to create a communication channel between cores.
STM32H745 、 STM32H755 、 STM32H747 、 STM32H757 、 STM32 、 STM32CubeH7 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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25-Feb-2021 |
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Rev 1 |
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AN5617 |
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259 KB |
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