STM32H745/755 and STM32H747/757 lines dual-core architecture Application note
■ Microcontrollers of the STM32H745/755 and STM32H747/757 lines feature an asymmetric dual‑core architecture to boost performance and to enable ultra-fast data transfers through the system while achieving major power savings and enhanced security.
■ These microcontrollers are based on the high-performance Arm® Cortex®-M7 and Cortex®-M4 32-bit RISC cores. The Arm® Cortex®-M7 (CPU1) is located in the D1 domain and operates up to 480 MHz. The Arm® Cortex®-M4 (CPU2) is located in the D2 domain and operates up to 240 MHz. The system is partitioned into three power domains that operate independently, thus obtaining the best trade-off between power consumption and core performance.
■ A specific development approach is needed to get the maximum advantage from the dual-core architecture: this document provides an overview of the MCUs dual-core architecture, as well as of their memory interfaces and features. It introduces an example based on STM32CubeMX tool, simple peripheral initialization without any communication between two cores. It also provides firmware examples to describe how to build a communication channel between cores, and send data from CPU2 to CPU1 using OpenAMP MW to create a digital oscilloscope (for FFT).
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STM32H745 、 STM32H755 、 STM32H747 、 STM32H757 、 STM32CubeMX 、 STM32H7 、 STM32 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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13-Nov-2020 |
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Rev 1 |
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AN5557 |
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1.4 MB |
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