STM32MP15x lines using low-power modes Application note
■STM32MP15x lines devices are built on an Arm® Cortex®-A7 with single or dual-core MPU subsystem combined with an Arm® Cortex®-M4 CPU.
■STM32MP15x devices can be configured in various low-power modes in order to reduce power consumption when necessary.
■This application note explains the various low-power modes of the STM32MP15x lines devices, and how to configure and exit from them. This document also presents some guidance to be considered when using low-power modes at system level, and when using an external STPMIC1x power regulator component.
●Overview:
■This application note is applicable to all the devices of the STM32MP15x lines. The table below describes their main characteristics.
■Depending on the device’s part number, the system includes a Cortex-M4 and either a single-core or a dual-core Cortex-A7. In this document, the Cortex-A7 is called MPU and the Cortex-M4 is called MCU.
The full featured system (see the table below) is partitioned in:
▲One MPU subsystem: dual Cortex-A7 with L2 cache
▲One MCU subsystem: Cortex-M4 with associated peripherals clocked according to CPU activity
■The present document assumes a full featured device (for example STM32MP157).
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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November 2020 |
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Rev 4 |
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AN5109 |
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1.1 MB |
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