PowerPC 603™ Hardware Interrupt Latency In Embedded Applications

2021-10-26
●By Wendell Smith, Paul Nelson, and Amy Dyson, High Performance Embedded Systems
●The PowerPC™ 603 microprocessor is a RISC design, achieving a high level of performance using instructionpipelining and a superscalar architecture. In addition to branch folding, two instructions may complete in a singlecycle and as many as five instructions may execute simultaneously. This parallelism complicates how quicklythe processor can service external interrupts. For example, when an external device requests an interrupt, astore may be pending; to maintain program coherency, that store must complete before the 603 branches tothe interrupt handler
●The PowerPC 603 microprocessor completes one instruction before recognizing an external interrupt. That oneinstruction may cause exceptions such as an illegal operation exception, delaying the handling of the externalinterrupt. We demonstrate that few of these instruction-caused exceptions occur in an embedded applicationas compared to a general desktop computing environment.
●In this paper, we examine the instruction flow, the interrupt recognition method, and interrupt latency factors ofthe PowerPC 603 microprocessor. We show that the instruction-caused exceptions do not affect the interruptresponse of most embedded applications. We suggest ways system designers can minimize interrupt latencyfor embedded applications. Finally, we describe how to use the PowerPC decrementer exception, as availablein the 603, to measure the hardware interrupt latency.

NXP

PowerPC 603

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microprocessor

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Application note & Design Guide

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