NB4N527S Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel & trade; to LVDS Receiver/Driver/Buffer, with Internal Termination
●NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating Any Level™ input signal (LVPECL, CML,HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.5 GHz, respectively.
●The NB4N527S has a wide input common mode range of GND + 50 mV to VCC− 50 mV combined with two 50 Ω internal termination resistors is ideal for translating differential or single−ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components (Figure 6).
●The device is offered in a small 3 mm x 3 mm QFN−16 package.NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.
●Features
■Maximum Input Clock Frequency up to 1.5 GHz
■Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
■470 ps Maximum Propagation Delay\
■1 ps Maximum RMS Jitter
■140 ps Maximum Rise/Fall Times
■Single Power Supply; V-CC = 3.3 V ±10%
■Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
■Internal 50 Ω Termination Resistor per Input Pin
■GND + 50 mV to V-CC− 50 mV V-CMR Range
■These are Pb−Free Devices
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Datasheet |
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Please see the document for details |
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QFN−16 |
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English Chinese Chinese and English Japanese |
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June, 2011 |
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Rev. 5 |
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NB4N527S/D |
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242 KB |
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