XD551 DIP8, XL551 SOP8 monolithic timing circuit
Like the XL555, the XDXL551 has a trigger level equal to approximately one-third of the supply voltage and athreshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low. the flip-flop is reset and the output is low Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA; the XDXL551 exhibits greatly reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling capacitors required by the XL555.
The XDXL551C is characterized for operation from 0 °C to 70°C.
● Very Low Power Consumption 1 mW Typ at V-DD = 5V
● Capable of Operation in Astable Mode
● CMOS Output Capable of Swinging Rail to Rail
● High Output-Current Capability Sink 100 mA Typ; Source 10 mA Typ
● Output Fully Compatible With CMOS, TTL, and MOS
● Low Supply Current Reduces Spikes During Output Transitions
● Single-Supply Operation From 1 V to 15 V
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Please see the document for details |
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DIP8;SOP8;SOP;DIP |
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English Chinese Chinese and English Japanese |
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523 KB |
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