SH3-DSP CPU 32-bit RISC CPU Datasheet
Key Features:
●Compatible with object code level with SH -1, SH -2, and SH 3
●Built-in 32-bit internal data bus
●Supports abundant register groups
■General-purpose register: Sixteen 32-bit registers (including eight 32-bit bank registers)
■Control register: Eight 32-bit registers
■System register: Four 32-bit registers
●The instruction execution time of the basic instruction corresponds to one instruction / cycle
●The logical address space corresponds to 4 GB
●Features of DSP
■Mixing 16-bit instructions and 32-bit instructions
■Supports multiplier, ALU, barrel shifter
■Built-in 32-bit one-cycle multiplier corresponding to 16 bits x 16 bits
■Supports large capacity DSP data register file
■Supports extended Harvard architecture for DSP data bus
●Peripheral circuit
■MMU, TLB, INTC, UBC, AUD, BSC, DMAC
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2019.10.30 |
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Rev.1.01 |
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R06PM0057EJ0101 |
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143 KB |
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