AN1227: Lock Time Parameters Affecting the Si534x/7x/8x/9x High Performance Jitter Attenuator Devices
The ability to power up and quickly generate a stable, accurate clock is critical in many applications. Other applications may have subsystems that are slow to initialize and therefore do not have a pressing need for a quick start. Similarly, some applications must be able to quickly switch between different operating modes on-the-fly, while other applications are less concerned with this capability. It is important to understand the demands of the PLL system to ensure that the device is configured appropriately to provide performance when needed while making the appropriate compromises that result in a practical and affordable solution. This application note explains the various parameters that affect how quickly the PLL can lock to an input clock and measures that can betaken to optimize lock time.
KEY FEATURES:
• Enabling fastlock or hitless switching and phase buildout on holdover exit are options to help optimize lock time.
•ClockBuilder™ Pro makes it easy to configure the device.
• Si5397/96/95/94/92/72/71/47/46/45/44/42.
• Si5386/82/81/80.
• Si5348.
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Si534x 、 Si537x 、 Si538x 、 Si539x 、 Si5397 、 Si5396 、 Si5395 、 Si5394 、 Si5392 、 Si5372 、 Si5371 、 Si5347 、 Si5346 、 Si5345 、 Si5344 、 Si5342 、 Si5386 、 Si5382 、 Si5381 、 Si5380 、 Si5348 、 Si5395A-EVB 、 Si5395A |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2020/03/26 |
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Rev. 0.1 |
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AN1227 |
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1.2 MB |
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