IDT Clock Buffers Offer Low Additive Phase Jitter APPLICATION NOTE
High performance clock buffers are widely used in digital consumer and communications applications for distribution of clock signals. A critical parameter for these buffers is additive phase noise that can degrade system performance and reliability. This application note briefly explains the theory behind measuring additive phase noise for IDT clock buffers and summarizes the additive phase jitter results for several widely used IDT clock buffers. Other AC parameters of interest for buffers are input to output propagation delay and output to output skew.
In synchronous systems where timing and performance of the system is dependent on the clock, integrity of the clock signal is important. Designers must optimize board layout, use clean power supplies and follow recommended decoupling and termination schemes for the outputs in order to meet the EMI and timing budgets for their application.
IDT has a large variety of low skew clock distribution devices to meet all your application needs. Figure 1 shows a typical set top box application where an IDT clock buffer is used to distribute 33MHz PCI clocks to multiple PCI slots.
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ICS553 、 IDT2305NZ 、 ICS551 、 IDT74FCT3807 、 IDT5T30533 |
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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12/03/13 |
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REVISION A |
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AN-804 |
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408 KB |
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