W956D8MBYA/ W956A8MBYA 64Mb HyperRAM
■ FEATURES
● Interface: HyperBus
● Power supply: 1 7V-2.0V or 2.7V-3.6V
● Maximum clock rate: 200MHz
● Double-Data Rate (DDR) Up to 400 MT/s
● Clock:
▲ Single ended clock (CK)
▲ Differential clock (CK/CK#)
● Chip Select (CS#)
● 8-bit data bus (DQ[7:0])
● Hardware reset (RESET#)
● Read-Write Data Strobe (RWDS)
▲ Bidirectional Data Strobe / Mask
▲ Output at the start of all transactions to indicate refresh latency
▲ Output during read transactions as Read Data Strobe
▲ Input during write transactions as Write Data Mask
● Performance and Power
▲ Configurable output drive strength
▲ Power Saving Modes
◆ Hybrid Sleep Mode
◆ Deep Power Down
▲ Configurable Burst Characteristics
◆ Linear burst
◆ Wrapped burst lengths:
◆ 16 bytes (8 clocks)
◆ 32 bytes (16 clocks)
◆ 64 bytes (32 clocks)
◆ 128 bytes (64 clocks)
◆ Hybrid burst - one wrapped burst followed by linear burst
◆ 64 Mbit only
▲ Array Refresh Modes
◆ Full Array Refresh
◆ Partial Array Refresh
▲ Support package: 24 balls TFBGA
▲ Operating temperature range: -40°C < TCASE < 85°C
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W956D8MBYA 、 W956A8MBYA 、 W956D8MBYA5I 、 W956D8MBYA6I 、 W956A8MBYA5I 、 W956A8MBYA6I |
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Datasheet |
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Please see the document for details |
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TFBGA |
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English Chinese Chinese and English Japanese |
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Sep. 25, 2019 |
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Revision: A01-001 |
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1.9 MB |
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