AS4C256M16D4 256M x 16 bit DDR4 Synchronous DRAM (SDRAM)

2020-04-26
The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight-banks
(2 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit
wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock
cycle data transfers at the I/O pins.
Read and write operation to the DDR4 SDRAM are burst oriented, start at a selected location, and continue
for a burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration of an Activate Command, which is then followed by a Read or Write command. The address bits registered coincident with the Activate Command are used to select the bank and row to be activated (BG0
select the bank group; BA0-BA1 select the bank; A0-A14 select the row). The address bits registered
coincident with the Read or Write command are used to select the starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10), and select BC4 or BL8 mode
‘on the fly’ (via A12) if enabled in the mode register.

Prior to normal operation, the DDR4 SDRAM must be powered up and initialized in a predefined manner.

The following sections provide detailed information covering device reset and initialization, register definition,
command descriptions, and device operation.

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Part#

256M x 16 bit DDR4 Synchronous DRAM (SDRAM)

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Datasheet

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Halogen Free 、 Pb Free 、 ROHS

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Please see the document for details

Commercial 、 Industrial

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96-ball FBGA

English Chinese Chinese and English Japanese

Aug 2019

Rev 1.0

10.5 MB

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