IDT® Tsi574 Serial RapidIO Switch
The successful implementation of a Tsi574 in a board design is dependent on properly routing the Serial RapidIO signals and maintaining good signal integrity with a resultant low bit error rate. The sections that follow contain information for the user on principals that will maximize the signal quality of the links.
Since every situation is different, IDT urges the designer to model and simulate their board layout and verify that the layout topologies chosen will provide the performance required of the product.
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Tsi574 、 TSI574-10GILV 、 TSI574-10GIL 、 TSI574-10GCLV 、 TSI574-10GCL 、 Tsi NNN(N)- SS(S)EPG(Z#) |
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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May 18, 2012 |
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2 MB |
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