S1D13A05 LCD/USB Companion Chip Hardware Functional Specification
This is the Hardware Functional Specification for the S1D13A05 LCD/USB Companion Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers.
1.2 Overview Description:
The S1D13A05 is an LCD/USB solution designed for seamless connection to a wide variety of microprocessors. The S1D13A05 integrates a USB slave controller and an LCD graphics controller with an embedded 256K byte SRAM display buffer. The LCD controller supports all standard panel types and multiple TFT types eliminating the need for an external timing control IC. The S1D13A05 includes a Hardware Acceleration Engine to greatly improve screen drawing functions and the built-in USB controller provides revision 1.1 compliance for applications requiring a USB client. This high level of integration provides a low cost, low power, single chip solution to meet the demands of embedded markets requiring USB client support, such as Mobile Communications devices and Palm-size PCs.The S1D13A05 utilizes a guaranteed low-latency CPU architecture that provides support for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data path, write buffer and the Hardware Acceleration Engine provide high performance bandwidth into display memory allowing for fast display updates.Additionally, products requiring a rotated display can take advantage of the SwivelViewTMfeature which provides hardware rotation of the display memory transparent to the software application. The S1D13A05 also provides support for “Picture-in-Picture Plus” (a variable size Overlay window).The S1D13A05, with its integrated USB client, provides impressive support for Palm OShandhelds. However, its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications.
Features:
2.1 Integrated Frame Buffer:
• Embedded 256K byte SRAM display buffer.
2.2 CPU Interface:
• Direct support of the following interfaces:
■Hitachi SH-4 / SH-3.
■Motorola M68xxx (REDCAP2, DragonBall, ColdFire).
■Motorola DragonBall SZ Support (66MHz).
■Motorola “REDCAP2” - no WAIT# signal.
■Generic MPU bus interface with programmable ready (WAIT#).
• “Fixed” low-latency CPU access times.
• Registers are memory-mapped - M/R# input selects between memory and register address space.
• The complete 256K byte display buffer is directly and contiguously available through the 18-bit address bus.
2.3 Display Support:
• Single-panel, single drive passive displays.
• 4/8-bit monochrome LCD interface.
• 4/8/16-bit color LCD interface.
• Active Matrix TFT interface.
• 9/12/18-bit interface.
• Extended TFT interfaces (Type 2, 3, 4)
• ‘Direct’ support for 18-bit Sharp HR-TFT LCD (or compatible interfaces).
• ‘Direct’ support for the Casio TFT LCD (or compatible interfaces).
2.4 Display Modes:
• 1/2/4/8/16 bit-per-pixel (bpp) color depths.
• Up to 64 gray shades on monochrome passive LCD panels.
• Up to 64K colors on passive panels.
• Up to 64K colors on active matrix LCD panels.
• Example resolutions:
■320x320 at a color depth of 16 bpp
■160x160 at a color depth of 16 bpp (2 pages)
■160x240 at a color depth of 16 bpp
2.5 Display Features:
• SwivelView™: 90°, 180°, 270° counter-clockwise hardware rotation of display image.
• Picture-in-Picture Plus (PIP+): displays a variable size window overlaid over back-ground image.
• Pixel Doubling: independent control of both horizontal and vertical pixel doubling.
• example usage: 160x160 8 bpp can be expanded to 320x320 8 bpp without any addi-tional memory.
• supports all color depths.
• Double Buffering/Multi-pages: provides smooth animation and instantaneous screen updates.
2.6 Clock Source:
• Three independent clock inputs: CLKI, CLKI2 and USBCLK.
• Flexible clock source selection:
• internal Bus Clock (BCLK) selected from CLKI, CLKI/2, or CLKI2
• internal Memory Clock (MCLK) selected from BCLK or BCLK divide ratio (REG[04h)
• internal Pixel Clock (PCLK) selected from CLKI, CLKI2, MCLK, or BCLK. PCLK can also be divided down from source
• Single clock input possible if USB support not required.
2.7 USB Device:
• USB Client, revision 1.1 compliant.
• Dedicated clock input: USBCLK.
• 48MHz crystal oscillator for USBCLK.
2.8 2D Acceleration:
• 2D BitBLT engine including:
■Write BitBLT ■Transparent Write BitBLT
■Move BitBLT ■Transparent Move BitBLT
■Solid Fill BitBLT ■Read BitBLT
■Pattern Fill BitBLT ■Color Expansion BitBLT
■Move BitBLT with Color Expansion
2.9 Miscellaneous:
• Software initiated Video Invert.
• Software initiated Power Save mode.
• General Purpose Input/Output pins are available.
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User's Guide |
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Please see the document for details |
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PFBGA |
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English Chinese Chinese and English Japanese |
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March 14, 2018 |
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Rev. 7.8 |
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X40A-A-001-07.8 |
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5.2 MB |
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