S1D13A05 LCD/USB Companion Chip Power Consumption
●S1D13A05 Power Consumption
■S1D13A05 power consumption is affected by many system design variables.
▲Input clock frequency (CLKI/CLKI2): the CLKI/CLKI2 frequency determines the LCD frame-rate, CPU performance to memory, and other functions – the higher the input clock frequency, the higher the frame-rate, performance and power consumption.
▲CPU interface: the S1D13A05 current consumption depends on the BCLK frequency, data width, number of toggling pins, and other factors – the higher the BCLK, the higher the CPU performance and power consumption.
▲V-DD voltage level: the voltage level affects power consumption – the higher the voltage, the higher the consumption.
▲Display mode: the resolution and color depth affect power consumption – the higher theresolution/color depth, the higher the consumption.
▲Internal CLK divide: internal registers allow the input clock to be divided before going to the internal logic blocks – the higher the divide, the lower the power consumption.
■The S1D13A05 supports a software initiated power save mode. The power consumption in power save mode is affected by various system design variables.
▲Clock states during the power save mode: disabling the clocks during power save mode has substantial power savings
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Technical Documentation |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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March 28, 2018 |
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Rev. 1.1 |
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X40A-G-006-01.1 |
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361 KB |
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