AS4C16M16MD1 256Mb MOBILE DDR SDRAM Data Sheet
as 8,192 rows by 512 columns by 16 bits, fabricated with Alliance Memory's high performance CMOS technology. This device uses a
double data rate architecture to achieve high- speed operation. The double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. Range of operating
frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high
bandwidth and high performance memory system applications.
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Datasheet |
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Halogen Free 、 Pb Free 、 ROHS 、 lead free |
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Please see the document for details |
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Commercial |
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FPBGA |
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English Chinese Chinese and English Japanese |
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Oct24, 2015 |
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Ver.1.1 |
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16 MB |
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