AS4C2GM4D3L AS4C1G8MD3L AS4C512M16D3L 8Gb: x4, x8, x16 DDR3L SDRAM Description Data Sheet
The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
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AS4C2GM4D3L 、 AS4C1G8MD3L 、 AS4C512M16D3L 、 AS4C2GM4D3L-12BCN 、 AS4C2GM4D3L-12BIN 、 AS4C1G8MD3L-12BCN 、 AS4C1G8MD3L-12BIN 、 AS4C512M16D3L-12BCN 、 AS4C512M16D3L-12BIN 、 AS4C1GM8D3L-12BCN 、 AS4C1GM8D3L-12BIN 、 AS4C512GM16D3L-12BCN 、 AS4C512GM16D3L-12BIN |
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256 Meg x 4 x 8 banks DDR3L SDRAM 、 128 Meg x 8 x 8 banks DDR3L SDRAM 、 64 Meg x 16 x 8 banks DDR3L SDRAM |
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Datasheet |
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Lead Free 、 Pb-free |
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Please see the document for details |
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Commercial 、 Industrial |
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FBGA |
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English Chinese Chinese and English Japanese |
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June 2016 |
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Rev2.0 |
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7.3 MB |
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