STM32MP157A Arm® dual Cortex®-A7 650 MHz + Cortex®-M4 MPU, 3D GPU, TFT/DSI, 37 comm. interfaces, 29 timers, adv. analog
■ Introduction
● This datasheet provides the ordering information and mechanical device characteristics of the STM32MP157Amicroprocessors.
● For information on the Arm®<3} Cortex®-A7 and Cortex®-M4 cores, refer to the Cortex's-A7 and Cortex®-M4 Technical Reference Manuals.
■ Description
● The STM32MP157Adevices are based on the high-performance Arm® Cortex®-AZ 32-bit RISC core operating at up to 650 MHz. The Cortex-A7 processor includes a 32-Kbyte L1 instruction cache, a 32-Kbyte L1 data cache and a 256-Kbyte Ievel2 cache. The Cortex-A7 processor is a very energy-efficient application processor designed to provide rich performance in high-end wearables, and other low-power embedded and consumer applications. It provides up to 20% more single thread performance than the Cortex-A5 and provides similar performance than the Cortex-A9.
● The Cortex-A7 incorporates all features of the high-performance Co_rtex-A15 and Cortex-A17 processors, including virtualization support in hardware, NEON and 128-bit AMBA®4 AXI bus interface.
● The STM32MP157Adevices also embed a Cortex® -M4 32-bit RISC core operating at up to 209 MHz frequency. Cortex-M4 core features a floating point unit (FPU) single precision which supports Anrr' single-precision data-processing instructions and data types. The Cortex® -M4 supports a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
● The STM32MP157Adevices provide an external SDRAM interface supporting external memories up to 8-Gbit density (1 Gbyte), 16 or 32-bit LPDDR2/LPDDR3 or DDR3/DDR3L up to 533 MHz.
● The STM32MP157Adevices incorporate high-speed embedded memories with 703 Kbytes of Internal SRAM (including 256 Kbytes of AXI SYSRAM, 3 banks of 128 Kbytes each of AHB SRAM, 64 Kbytes of AHB SRAM in backup domain and 4 Kbytes of SRAM in backup
domain), as well as an extensive range of enhanced l/Os and peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix and a 64-bit multi layer AXI interconnect supporting internal and external memories access.
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STM32MP157A 、 STM32 、 STM32MP157AAA3T 、 STM32MP157x 、 STM32MP157AADxx 、 STM32MP157AABxx 、 STM32MP157AACxx 、 STM32MP157AAAxx |
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Datasheet |
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Please see the document for details |
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LFBGA448;TFBGA361;LFBGA354;TFBGA257 |
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English Chinese Chinese and English Japanese |
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February 2019 |
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Rev 1 |
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DS12504 |
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7 MB |
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