DEIC420 And IXDD415 Spice Model
●The following application note describes a PSpice model for the DEIC420 and IXDD415 gate driver ICs. This model was developed using Pspice Plugin version 9.2.3.268.
●Referring to the schematic below, Vi is a pulse voltage source. TD, TR and TF should not be changed from their present settings. The IXDD415 is comprised of two of the models given in this document.
●C1 and R1 allow for the internal power consumption as shown in Figures 6 and 7 of the DEIC420 data sheet. L1 and R2 model the internal impedance of the device. C2, L2, and R3 model internal strays of the DEIC420. R4 is necessary to insure that PSpice functions properly if the load is removed.
●The load is comprised of C3, L3 and R5. C3 is the specified load capacitance. L3 and R5 represent the stray terms Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR).
●At the switching speed and operating frequency of the DEIC420 the inclusion of these stray terms is essential for proper device modeling. The average of the C1 Vprobe and the R1 Iprobe provide the consumed power and the C3 Vprobe provides a measurement of the output voltage.
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2003 |
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REV 1 |
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Doc#9300-0010 |
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127 KB |
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