Analysis of Classic MOS Tube Drive Circuit

PublishTime： 2024-02-12 Article Source：HI-SEMICON News Author：Shenzhen Hi-semicon Electronics CO.,LTD

power device MOS tube,MOS tube,NMOS,high-voltage MOS tube

When making a power supply or drive, a power device MOS tube is the most commonly used device. When using an MOS tube, if some parameters of the MOS tube are not carefully considered, the circuit is usually unable to work.

MOS tubes are widely used in circuits we are familiar with, such as switching power supplies, electric motors, lighting dimming, and other driving circuits. In this application, we generally use low-voltage MOS tubes. The high-voltage MOS tube is corresponding to the low-voltage MOS tube. The classification of these two MOS tubes is based on voltage. Generally, the voltage of the high-voltage MOS tube is around 400V-1000V, which can provide effective lock protection operation. The use of CMOS technology, compared with the bipolar driver, has low power consumption, and high operating efficiency, and can also improve the reliability of the system. Low voltage MOS tube voltage around 1V-40V, high speed, high performance, low power consumption, low on-resistance, small package, and other advantages, suitable for protection circuit and switching circuit.

Today's MOS drivers have several special applications:
1. Low-voltage application: when a 5V power supply is used, if a traditional totem pole structure is used at this time, the voltage drop of the BE audion is about 0.7V, resulting in the actual voltage finally added to the gate being only 4.3V. At this time, there is a certain risk when we choose THE MOS tube with a nominal GATE voltage of 4.5V. The same problem occurs with 3V or other low-voltage sources.

2. Wide voltage applications: The input voltage is not a fixed value, it will change with time or other factors. This change causes the drive voltage supplied by THE PWM circuit to the MOS tube to be unstable.

To make MOS tubes safe under high gate voltage, many MOS have voltage regulators installed in the tubes to forcibly limit the amplitude of gate voltage. In this case, when the supplied driving voltage exceeds the voltage of the regulator tube, a large static power consumption will be caused.

At the same time, if we simply reduce the GATE voltage by using the principle of resistor divider, the MOS tube will work well when the input voltage is high, but when the input voltage is low, the GATE voltage is insufficient, causing insufficient conduction and thus increasing the power consumption.

3. Dual voltage applications: In some control circuits, the logic portion USES a typical digital voltage of 5V or 3.3V, while the power portion USES a voltage of 12V or more. The two voltages are connected in common ground mode. This requires the use of a circuit so that the low-voltage side can effectively control the HIGH-voltage side of the MOS tube. Meanwhile, the high-voltage side of the MOS tube will also face the problems mentioned in 1 and 2.

In these three cases, the totem pole structure can not meet the output requirements, and for many off-the-shelf MOS drive ICs, it seems that there is no structure containing a gate voltage limit. Two relatively common circuits are Shared to satisfy the above three application scenarios.
The circuit diagram is as follows:

Fig.2Drive circuit for NMOS

Fig.3 Driver circuit for PMOS

The NMOS and PMOS drive circuits in the figure above have the same function. Here, only the NMOS drive circuit is analyzed:
V_L and V_H are low-end and high-end power supplies respectively. The two voltages can be the same, but V_L should not exceed V_H.

Q1 and Q2 form an inverted totem pole to achieve isolation while ensuring that the two drive tubes Q3 and Q4 do not simultaneously conduct.

R2 and R3 provide PWM voltage reference, and by changing this reference, the circuit can be operated in the position where THE PWM signal waveform is relatively steep.

Q3 and Q4 are used to provide driving current. When conducting, both Q3 and Q4 have a minimum V_CE drop relative to V_H and GND, which is usually only about 0.3V, much lower than the 0.7V V_CE.

R5 and R6 are feedback resistors, which are used to sample gate voltage. The sampled voltage generates strong negative feedback to the base of Q1 and Q2 through Q5, thus limiting gate voltage to a limited value. This value can be adjusted by R5 and R6.

Finally, R1 provides the base current limit of Q3 and Q4, and R4 provides the gate current limit of the MOS tube, namely the limit of Ice of Q3 and Q4. If necessary, the capacitors can be accelerated in parallel on R4.

This circuit provides the following features:

Drive high-end MOS tube with low voltage and PWM;

MOS tube with high GATE voltage requirement is driven by a small amplitude PWM signal;

Gate voltage peak limit;

Current limits for input and output;

By using the right resistance, very low power consumption can be achieved;

PWM signal reverse phase. NMOS does not require this feature and can be solved by prefacing an inverter.

Totem poles have been mentioned many times, but here's what totem poles are.

Fig.4

The totem pole is a transistor on the upper and lower sides, the upper tube is NPN, the c pole is connected to the positive power supply, the lower tube is PNP, the E pole is connected to the negative power supply, note, is the negative power supply, is the ground. Two B poles are connected for input, e of the upper pipe, and C of the lower pipe are connected for output. Used to match voltage, or improve IO port drive capability.

As the above circuit analysis, the use of an MOS tube involves a lot of knowledge points, I hope you can correctly standardize the use of an MOS tube, and give play to its maximum value.

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