Agilent E5910A Serial Link Optimizer for Xilinx FPGAs
Agilent’s E5910A serial linkoptimizer solution begins withXilinx’s ChipScope Pro Serial I/OToolkit, which provides theinfrastructure required to specifyand implement a bit error ratiotest (BERT) core that is placed inyour FPGA. This internal BERT(IBERT) core provides thenecessary functions to implementa BER test on the MGTs youspecify, and it includes the abilityto access the transmitter andreceiver equalization settings inreal-time. Using this IBERT core,Agilent’s serial link optimizersoftware communicates with thecore via JTAG (using the Xilinxcable) to make measurements andcontrol the MGT transmitter andreceiver settings.This measurement systemarchitecture (see Figure 1)requires no external hardwareother than the standard Xilinxdownload cable, which minimizesyour costs. Using an internal testcore also allows you to measurepost-equalization BER at theon-chip receiver input (asopposed to the pins of the devicefor a typical BER measurement).This approach means you can see the true effect of equalizationsettings on your link design andtest and characterize itsoperation more reliably.
[ Xilinx FPGAs ] |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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January 24, 2007 |
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Revised: 11/08/06 |
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5989-5969EN |
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493 KB |
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