CD4051BMS, CD4052BMS, CD4053BMS CMOS Analog Multiplexers/Demultiplexers* DATASHEET
are digitally controlled analog
switches having low ON impedance and very low OFF leakage
current. Control of analog signals up to 20V peak-topeak
can be achieved by digital signal amplitudes of 4.5V to
20V (if VDD-VSS = 3V, a VDD-VEE of up to 13V can be controlled;
for VDD-VEE level differences above 13V, a VDDVSS
of at least 4.5V is required). For example, if VDD =
+4.5V, VSS = 0, and VEE = -13.5V, analog signals from -
13.5V to +4.5V can be controlled by digital inputs of 0 to 5V.
These multiplexer circuits dissipate extremely low quiescent
power over the full VDD-VSS and VDD-VEE supply voltage
ranges, independent of the logic state of the control signals.
When a logic “1” is present at the inhibit input terminal all
channels are off.
The CD4051BMS is a single 8 channel multiplexer having
three binary control inputs, A, B, and C, and an inhibit input.
The three binary signals select 1 of 8 channels to be turned
on, and connect one of the 8 inputs to the output.
The CD4052BMS is a differential 4 channel multiplexer having
two binary control inputs, A and B, and an inhibit input.
The two binary input signals select 1 of 4 pairs of channels to
be turned on and connect the analog inputs to the outputs.
The CD4053BMS is a triple 2 channel multiplexer having
three separate digital control inputs, A, B, and C, and an
inhibit input. Each control input selects one of a pair of channels
which are connected in a single pole double-throw configuration.
The CD4051BMS, CD4052BMS and CD4053BMS are supplied
in these 16 lead outline packages:
Braze Seal DIP *H4X †H4T
Frit Seal DIP H1E
Ceramic Flatpack H6W
*CD4051B Only †CD4052B, CD4053 Only
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CD4051BMS 、 CD4052BMS 、 CD4053BMS 、 CD4051BMSH 、 CD4052BMSH 、 CD4053BMSH |
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CMOS Signal 8-Channel Analog Multiplexers/Demultiplexers 、 CMOS Differential 4-Channel Analog Multiplexers/Demultiplexers 、 CMOS Triple 2-Channel Analog Multiplexers/Demultiplexers |
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[ Analog and Digital Multiplexing and Demultiplexing ][ A/D and D/A Conversion ][ Signal Gating ] |
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Datasheet |
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ISO9001 |
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Please see the document for details |
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DIP;Flatpack |
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English Chinese Chinese and English Japanese |
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December 1992 |
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Rev 0.00 |
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FN3316 |
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713 KB |
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