ZL30111 POTS Line Card PLL Data Sheet
●Description
◆The ZL30111 POTS line card PLL contains a digital phase-locked loop(DPLL),which provides timing and synchronization for SLIC/CODEC devices.
◆The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference. It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable.
●Features
◆Synchronizes to 8 kHz,2.048 MHz,8.192 MHz or 19.44 MHz input
◆Provides a range of clock outputs:2.048 MHz,4.096 MHz and 8.192 MHz
◆Provides 2 styles of 8 kHz framing pulses
◆Automatic entry and exit from freerun mode on reference fail
◆Provides DPLL lock and reference fail indication
◆DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
◆Less than 0.6 ns-pp intrinsic jitter on all output clocks
◆20 MHz external master clock source:clock oscillator or crystal
◆Simple hardware control interface
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Datasheet |
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Please see the document for details |
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64 Pin TQFP;64 Pin TQFP* |
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English Chinese Chinese and English Japanese |
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January 2007 |
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592 KB |
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