EM74HC74; EM74HCT74 Dual D-type flip-flop with set and reset; positive edge-trigger
■The EM74HC74 and EM74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, is stored in the flip-flop and appears at the nQ output. Schmitt- trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC .
●Features and Benefits
■Wide operating voltage 2.0 V to 6.0 V
■High noise immunity
■CMOS low power dissipation
■Input levels:
◆For EM74HC74: CMOS level
◆For EM74HCT74: TTL level
■Symmetrical output impedance
■Balanced propagation delays
■Latch-up performance exceeds 100 mA
■Complies with JEDEC standard:
◆JESD8C (2.7 V to 3.6 V)
◆JESD7A (2.0 V to 6.0 V)
■ESD protection:
◆HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 3500 V
◆CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 2000 V
■Multiple package options
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EM74HC74D 、 EM74HCT74D 、 EM74HC74PW 、 EM74HCT74PW 、 EM74HC74 、 EM74HCT74 |
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dual positive edge triggered D-type flip-flop 、 Dual D-type flip-flop |
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Datasheet |
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Please see the document for details |
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SOP-14L;TSSOP14L |
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English Chinese Chinese and English Japanese |
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Apr 24, 2024 |
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Rev. 0.9 |
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1.4 MB |
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