XY_SCALER Digital Video Scaler IP Core
■Synthesizable, technology independent soft IP Core for FPGA, ASIC and SoC devices
■Supplied as human readable VHDL (or Verilog) source code
■Versatile RGB (or YCbCr 444) video scaler capable of scaling up or down by any factor
■Fully programmable scale parameters and scaler bypass function
■Fully programmable RGB channel widths allow support for any RGB format (or greyscale if only one channel is used)
■Supports all video resolutions up to 216 x 216 pixels
■Fully pipelined architecture with simple data-streaming flow control
■Features a 5x5-tap polyphase filter in the x and y dimensions with 16 unique phases
■Example general purpose 'Lanczos2' filter coefficients shipped with the design. Different coefficient sets available on request
■Output rate is 1 x pixel per clock for scaling factors > 1
■Generates one scaled output frame for every input frame
■No frame buffer required
■Supports 350MHz+ operation on basic FPGA devices
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[ flat panel displays ][ portable devices ][ video image sensors ][ consoles ][ video format converters ][ set-top boxes ][ digital TV ] |
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Datasheet |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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02/06/2022 |
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Rev. 3.2 |
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321 KB |
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