SA5Z-50 ARM STAR User Guide
■The STAR processor is a low gate count, highly energy efficient processor that is intended for microcontroller and deeply embedded applications. The processor is based on the Armv8‑M architecture and is primarily for use in environments where security is an important consideration. It is intended for deeply embedded applications that require optimal interrupt response features.
■The STAR Block integrated in SEAL incorporates following features:
▲Architecture: ARMv8-M(Harvard)
▲ISA Support: Thumb/Thumb-2
▲Pipeline: 3-stage + branch speculation
▲Dhrystone: 1.25 DMIPS/MHz
▲Interrupts : Non-maskable Interrupt(NMI) + 65 physical interrupts
▲Interrupt Latency: 12 cycles
▲Inter-Interrupt Latency: 6 cycles
▲Interrupt Priority Levels: 8 priority levels
▲Sleep: supported
▲Deep Sleep Mode: unsupported Currently
▲Bit Manipulation: Integrated Instructions & Bit Banding
▲Enhanced Instructions: Hardware Divide(2-12 Cycles) & Single-Cycle (32x32) Multiply
▲Debug: JTAG & Serial-Wire(SW) Debug Ports
▲Trace Components: MTB,ITM, DWT, TPIU,CTI
▲Max Core clock Frequency: 250MHz
▲BUS Matrix Protocol: AHB-Lite
▲Instruction Code SRAM: 256KB
▲Data SRAM: 192KB
▲Code/Date SRAM partially remapped as Instruction SRAM Supported
▲Timer x2
▲DualTimer x2
▲UART x3
▲SPI(Master) x1、x2、x4
▲I2C(Master) x1
▲WatchDog x1
▲ADC x2
▲GPIO(32-bits) x1
▲AHB-Lite Slave Port x2 (Ports connected to Fabric)
▲AHB-Lite Master Port x2 (Ports connected to Fabric)
▲DMAC x1
▲DSP : Pack halfworld 、 Saturating 、 Arithmetic 、 Reverse bit/bytes 、 select bytes 、 SIMD 、 Extetend multiply
▲FPU: single-precision data-processing、double-precision load and store
▲MPU 8
▲ICACHESZ 8KB
▲DCACHESZ 8KB
▲MTB memory 2KB
▲Coprocessor 8
▲WIC
▲QSPI
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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20231102 |
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Version 1.0 |
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UG05205 |
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7.6 MB |
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