Embedded Peripherals IP User Guide
●Introduction
■This user guide describes the IP cores provided by Quartus® Prime design software. The IP cores are optimized for Intel® FPGA devices and can be easily implemented to reduce design and test time. You can use the IP parameter editor from Platform Designer to add the IP cores to your system, configure the cores, and specify their connectivity.
■Before using Platform Designer, review the Quartus Prime software Release Notes for known issues and limitations. To submit general feedback or technical support, click Feedback on the Quartus Prime software Help menu and also on all Intel FPGA technical documentation.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2024.04.01 |
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6.7 MB |
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