Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon- MM) Interface for PCI Express User Guide
●Arria® 10 or Cyclone® 10 GX Avalon-MM Interface for PCIe Datasheet
■Arria® 10 and Cyclone® 10 GX FPGAs include a configurable, hardened protocol stack for PCI Express that is compliant with PCI Express Base Specification 3.0 and PCI Express Base Specification 2.0 respectively.
■The Hard IP for PCI Express IP core using the Avalon® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Packet (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in soft logic. It is available in Platform Designer.
|
|
|
|
User's Guide |
|
|
|
|
Please see the document for details |
|
|
|
|
|
|
|
|
|
|
|
English Chinese Chinese and English Japanese |
|
|
2024.04.13 |
|
|
|
|
|
|
|
|
2 MB |
- +1 Like
- Add to Favorites
Recommend
All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.
Integrated Circuits
Discrete Components
Connectors & Structural Components
Assembly UnitModules & Accessories
Power Supplies & Power Modules
Electronic Materials
Instrumentation & Test Kit
Electrical Tools & Materials
Mechatronics
Processing & Customization
