XM25QH10B 3V 1M-BIT SERIAL NOR FLASH WITH DUAL AND QUAD SPI
●GENERAL DESCRIPTION
■The XM25QH10B of non-volatile flash memory device supports the standard Serial Peripheral Interface (SPI). Traditional SPI single bit serial input and output (Single I/O or SIO) is supported as well as optional two bit (Dual I/O or DIO) and four bit (quad I/O) serial protocols. This multiple width interface is called SPI Multi-I/O or MIO.
■The SPI protocols use only 4 to 6 signals:
▲Chip Select (CS#)
▲Serial Clock (CLK)
▲Serial Data
◆IO0 (DI)
◆IO1 (DO)
◆IO2 (WP#)
◆IO3 (HOLD# / RESET#)
■The XM25QH10B support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-clocks instruction cycle Quad Peripheral Interface: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1(DO), I/O2 (WP#), and I/O3 (HOLD# / RESET#). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation.
■A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device ID and SFDP Register, a 64-bit Unique Serial Number and three 256-bytes Security Registers.
■The XM25QH10B provides an ideal storage solution for systems with limited space, signal connections,and power. These memories' flexibility and performance is better than ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly (XIP), and storing reprogrammable data.
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Datasheet |
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Please see the document for details |
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SOP;USON |
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English Chinese Chinese and English Japanese |
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2020/4/24 |
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Rev. A |
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1.7 MB |
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