CW32W031 ARM® Cortex®-M0+ Low-power wireless 32-bit MCU Reference Manual

2023-12-28
■System architecture
●The consists of CW32W031 microcontroller system contains:
▲2 master device:
◆ARM® Cortex®-M0+ core
◆General-purpose DMA
▲Multiple slave device:
◆On-chip SRAM
◆On-chip FLASH
◆FLASH controller
◆CRC redundancy calculation unit
◆GPIO port
◆AHB to APB1 conversion bridge and all devices on the APB1 bus
◆AHB to APB2 conversion bridge and all devices on the APB2 bus
◆AHB to APB3 conversion bridge and all devices on the APB3 bus
◆AHB to APB4 conversion bridge and all devices on the APB4 bus

CW

CW32W031CW32W031 seriesCW32W031R8U6-QFN64

More

Part#

ARM® Cortex®-M0+ Low-power wireless 32-bit MCUMCUmicrocontroller system

More

More

User's Guide

More

More

Please see the document for details

More

More

QFN64

English Chinese Chinese and English Japanese

May 18, 2023

Rev 1.0

23.7 MB

- The full preview is over. If you want to read the whole 573 page document,please Sign in/Register -
  • +1 Like
  • Add to Favorites

Recommend

All reproduced articles on this site are for the purpose of conveying more information and clearly indicate the source. If media or individuals who do not want to be reproduced can contact us, which will be deleted.

Contact Us

Email: