RS2CG572 Clock Generator Datasheet
●The RS2CG572 is a PLL based clock Generator for use in Ethernet applications. The device has optimal high clock frequency and low phase noise performance, combined with a low power consumption and high power supply noise rejection. Using RSM’s latest PLL technology, the RS2CG572 achieves <0.3ps RMS phase jitter performance.
●RS2CG572 can synthesize 100MHz, 125MHz, 156.25MHz and a low frequency 33.33MHz CPU clock from a single device. Six LVCMOS outputs also serve as additional buffering of the 50MHz crystal reference.
■Features
●Seven single-ended LVCMOS outputs, 30Ω output impedance
●Three LVPECL output pairs
▲One differential LVPECL (QA, nQA) output pair:156.25MHz
▲Two selectable differential LVPECL output pairs (QB, nQB and QC, nQC): 100MHz and 125MHz
●One single-ended LVCMOS (QD0) 33.33MHz CPU clock
●Selectable external crystal or single-ended input source
●Crystal oscillator interface designed for 50MHz, parallel resonant crystal
●Provides low jitter, high frequency output
●VCO frequency: 2.5GHz
●RMS phase jitter @ 125MHz, using a 50MHz crystal (12kHz – 20MHz): 0.256ps (Typ.)
●Power supply noise rejection PSNR: -80dB
●3.3V supply voltage
●-40°C to 85°C ambient operating temperature
●Lead-free (RoHS 6) packaging
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Datasheet |
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Please see the document for details |
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TQFN-40L |
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English Chinese Chinese and English Japanese |
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2023/9/18 |
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Revision 0.9 |
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RSM-DS-R-0053 |
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2.1 MB |
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