CMS32L032 Reference Manual Low power 32-bit microcontroller based on ARM® Cortex®-M0+
●This chapter provides a brief introduction to the features and debugging features of the ARM Cortex-M0+ core. For details, please refer to the ARM related documentation.
■Cortex-M0+ core features
●ARM Cortex-M0+ processor is a 32-bit RISC core with a 2-stage pipeline that supports privileged and user modes
●32-cycle hardware multiplier
●Nested vector interrupt controller (NVIC)
▲1 non-maskable interrupt (NMI)
▲Support 32 maskable interrupt requests (IRQ)
▲4 interrupt priority levels
●System Timer (SysTick) is a 24-bit countdown timer with a choice of FCLK or FIL count clock
●Vector table offset register (VTOR)
▲The software can write VTOR to relocate the vector table start address to a different location.
▲The default value of this register is 0x0000_0000, the lower 8 bits are ignored for writing and zero for reading, which means the offset is 256 bytes aligned.
■Debugging features
●2-wire SWD debug interface
●Support for suspending, resuming and single-step execution of programs
●Access to the processor's core registers and special function registers
●4 hardware breakpoints (BPU)
●Unlimited software breakpoints (BKPT instruction)
●2 data observation points (DWT)
●Accessing memory while the core is executing
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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August 2023 |
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V1.0.2 |
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28.9 MB |
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