MeiG SLM130-G(CG4A) SPI module
■Serial Peripheral Interface (SPI) bus is a high-speed full-duplex synchronous Serial communication Interface, which is widely used for information exchange between MCU and Peripheral devices with high communication rate requirements.
■The SPI interface uses four lines, which are:
▲MOSI - Data line MOSI - Master device Output/Slave device Input (SPI Bus Master Output/Slave Input)
▲MISO - Data line A Master device Input/Slave device Output (SPI Bus Master Input/Slave Output)
▲CLK - Serial Clock (Serial Clock), which outputs Clock signals from the primary device to the secondary device
▲SS - Slave select line, also called NSS, CS, etc., in which the master outputs a select-signal to the Slave.
■SPI works in master-slave mode, and typically a master device can be connected to one or more slave devices. The SPI controller corresponds to the SPI master device. The slave devices mounted on the same SPI controller share three signal pins: SCK, MISO, and MOSI, but the CS pins of each slave device are independent. When an SPI master device is connected to multiple slave devices, the communication is initiated by the master device, and the master device performs chip selection on the slave device by controlling the CS pin, which is generally effective at low level. Then, the clock signal is provided to the slave device through SCLK, the data is output to the slave device through MOSI, and the data sent by the slave device is received through MISO. At the same time, only one CS pin on an SPI master device is in a valid state, and the slave device connected to the valid CS pin can communicate with the master device at this time.
■SPI has four Polarity modes, mostly based on the Phase relationship between CPOL(Clock Polarity) and CPHA (Clock Phase). CPOL refers to the SCK level when the device is idle (before SPI communication starts and the NSS signal is at a high level). If CPOL=0, the SCK is low when it is idle. If CPOL=1, the SCK is low when it is idle. CPHA refers to the signal sampling time on the MOSI or MISO data line. When CPHA=0, it will be sampled on the "first jump edge (odd edge)" of the SCK clock line. When CPHA=1, the data line is sampled at the "second jump edge (even edge)" of SCK.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2022-08-01 |
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V1.0 |
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3 MB |
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