XC167CI-32F 16-Bit Single-Chip Microcontroller with C166SV2 Core
●Summary of Features
■High Performance 16-bit CPU with 5-Stage Pipeline
▲25 ns Instruction Cycle Time at 40 MHz CPU Clock (Single-Cycle Execution)
▲1-Cycle Multiplication (16 × 16 bit), Background Division (32 / 16 bit) in 21 Cycles
▲1-Cycle Multiply-and-Accumulate (MAC) Instructions
▲Enhanced Boolean Bit Manipulation Facilities
▲Zero-Cycle Jump Execution
▲Additional Instructions to Support HLL and Operating Systems
▲Register-Based Design with Multiple Variable Register Banks
▲Fast Context Switching Support with Two Additional Local Register Banks
▲16 Mbytes Total Linear Address Space for Code and Data
▲1024 bytes On-Chip Special Function Register Area (C166 Family Compatible)
■16-Priority-Level Interrupt System with 77 Sources, Sample-Rate down to 50 ns
■8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
■Clock Generation via on-chip PLL (factors 1:0.15 … 1:10), or via Prescaler (factors 1:1 … 60:1)
■On-Chip Memory Modules
▲2 Kbytes On-Chip Dual-Port RAM (DPRAM)
▲4 Kbytes On-Chip Data SRAM (DSRAM)
▲6 Kbytes On-Chip Program/Data SRAM (PSRAM)
▲256 Kbytes On-Chip Program Memory (Flash Memory)
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XC167CI-32F 、 C166SV2 、 XC167 、 SAK-XC167CI-32F40F 、 SAK-XC167CI-32F20F 、 SAF-XC167CI-32F40F 、 SAF-XC167CI-32F20F |
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Datasheet |
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Please see the document for details |
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P-TQFP-144-19;PG-TQFP-144-7 |
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English Chinese Chinese and English Japanese |
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2006-08 |
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V1.1 |
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2.1 MB |
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