BAT32G137 User Manual Ultra-low power 32-bit microcontroller based on ARM® Cortex®-M0+
■ARM Cortex-M0+ processors are 32-bit RISC cores with a 2-stage pipeline that supports privileged and user modes
■Memory Protection Units (MPUs) support 8 separate Zone (region) protection
■single cycle hardware multiplier
■Nested Vector Interrupt Controller (NVIC)
▲1 Unshielded Interrupt (NMI)
▲Supports 32 Masking Interrupt Requests (IRQs)
▲4 interrupt priority
■The system timer SysTick is a 24-bit countdown timer that can be selected for fCLK or fIL count clocks
■vector table offset register (VTOR)
▲The software can write VTOR to relocate the start address of the vector table to a different location
▲The default value for this register is 0x0000_0000, with low 8-bit write ignore, read to zero, that is, offset 256 bytes aligned
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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2023.2.27 |
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Rev.2.1.0 |
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55.5 MB |
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