F60C1A0002-M6 DDR3L x16 2Gb FORESEE® Industrial DDR3L Datasheet

2023-03-13
●Device Features
■Density: 2G bits
■Organization
▲128Meg x 16 bits
■Package
▲96-ball FBGA
▲Lead-free (RoHS compliant) and Halogen-free
■Power supply
▲VDD/VDDQ =1.35V (1.283 to 1.45V)
▲Backward compatible DDR3 (1.5V) operation
■Data Rate:
▲1600Mbps/1866Mbps
■2KB page size (x16)
▲Row address: A0 to A13
▲Column address: A0 to A9
■Eight internal banks for concurrent operation
■Burst lengths (BL): 8 and 4 with Burst Chop (BC)
■Burst type (BT)
▲Sequential (8, 4 with BC)
▲Interleave (8, 4 with BC)
■CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
■CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10
■Auto precharge option for each burst access
■Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)
■Refresh: auto-refresh, self-refresh
■Average refresh period
▲7.8us at TC ≤ +85°C
▲3.9us at +85°C ≤TC ≤ +95°C
■Operating temperature range
▲TC = 0°C to +85°C (Commercial Grade)
▲TC = -40°C to +95°C (Industrial Grade)
■The high-speed data transfer is realized by the 8bits prefetch pipelined architecture
■Double data-rate architecture: two data transfers per clock cycle
■Bi-directional differential data strobe (DQS and DQS#) is transmitted/received with data for capturing data at the receiver
■DQS is edge-aligned with data for READs; center aligned with data for WRITEs
■Differential clock inputs (CK and CK#)
■DLL aligns DQ and DQS transitions with CK transitions
■Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
■Data mask (DM) for write data
■Posted CAS by programmable additive latency for better command and data bus efficiency
■On-Die Termination (ODT) for better signal quality
■Synchronous ODT
■Dynamic ODT
■Asynchronous ODT
■Multi-Purpose Register (MPR) for pre-defined pattern read out
■ZQ calibration for DQ drive and ODT Access
■Programmable partial array self-refresh (PASR)
■RESET pin for Power-up sequence and reset function
■SRT (Self Refresh Temperature) range
■Normal/Extended/ASR
■Programmable output driver impedance control
■JEDEC compliant DDR3
■RH-Free (Row Hammer Free) option is available

FORESEE

F60C1A0002-M6ARF60C1A0002-M69WF60C1A0002-M6

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DDR3 SDRAM

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Industrial ]

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FBGA 96

English Chinese Chinese and English Japanese

2022/02/23

Rev. 1.3

2.9 MB

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