Renesas RA Family: RA Ethernet Design and Custom PHY Setup using FSP
■This application note describes Ethernet designs in general, provides a brief introduction to the RA Ethernet controller and interface to the PHY peripheral. It provides the design guidelines, when using the RA MCU with RMII modes for Ethernet specific applications.
■The app note also covers the usage of FSP configurator to add the Ethernet module and configure it correctly. Additionally, it covers the adding new PHY to custom boards and software support using FSP.
■App note also covers the usage of Wake-on-LAN (WOL) feature and using the LPM mode in Ethernet based designs. Finally, debugging of an Ethernet design based on RA is covered.
●Applies to:
■RA MCU Group with Ethernet Peripherals
●Introduction to Ethernet Connectivity
■Ethernet connectivity is one of the commonly used technologies in the data communications space, typically using a Local Area Network (LAN). Ethernet is based on the IEEE 802.3 standards supporting different speeds and mediums on which it runs. In recent years, Ethernet communication is used in home automation, industrial automation, and consumer electronics products. Ethernet is also used extensively in IoT applications as the default connectivity option. In Power over Ethernet (POE) based systems, power for the system can be derived from the communication line, without additional power connections for the system, which enables Ethernet as a perfect choice of connectivity for variety of applications as well.
●General Overview
■For networking connectivity challenges, Renesas Microcontrollers (MCUs) and Microprocessors (MPUs) with Ethernet support make it easy to implement Ethernet solution in your applications.
■The Renesas RA group of microcontrollers (MCUs) uses the high-performance Arm ® Cortex ® core and offers Ethernet MAC with built in DMA, to ensure high data throughput.
■Renesas RA Ethernet provides the following functionality:
▲10BASE-T/100BASE-TX IEEE 802.3 Compliant Ethernet
▲Half- and full-duplex support
▲Transmit/receive processing (Blocking and Non-Blocking)
▲Auto-negotiation support
▲Magic packet (Magic Pattern) detection mode support
▲Flow control compliant with IEEE802.3x
▲Media Independent Interface (MII), Reduced Media Independent Interface (RMII), compliant with the
▲IEEE802.3u standard
▲MDC/MDIO Management Interface for PHY Register Configuration
▲Wake-on-LAN (WOL) signal output
▲Hardware filtering of received multicast packets with a M
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Application note & Design Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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Oct.06.22 |
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Rev.1.00 |
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R01AN6628EU0100 |
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1.6 MB |
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