ESP32 Technical Reference Manual
●Introduction
■The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
■With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning they use the same addresses to access the same memory. Multiple peripherals in the system can access embedded memory via DMA.
■The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however for most purposes the two CPUs are interchangeable.
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User's Guide |
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Please see the document for details |
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English Chinese Chinese and English Japanese |
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August 31, 2016 |
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V1.0 |
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1.5 MB |
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