W7500 chip
●Features
▲ARM Cortex-M0:48MHz maximum frequency
▲Hardwired TCP/IP Core:8 Sockets;SRAM for socket:32 KB;MII (Medium-Independent Interface)
▲Memories
■Flash:128 KB
■Large flexible-size SRAM buffer for various User Application:Min 16KB available if full 32KB socket buffer used;Max 48KB available if no socket buffer used
■ROM for boot code: 6 KB
▲Clock,reset and supply management
■POR (Power-On Reset)
■Internal Voltage Regulator:3.3V to 1.5V
■8-to-24MHz external crystal oscillator
■Internal 8MHz RC Oscillator
■PLL for CPU clock
■32 kHz oscillator for RTC
▲ADC:12bit,8ch,1Msps
▲DMA:6-channel DMA controller;Peripheral supported:UARTs,SPIs
▲GPIO
▲53 I/Os (16 IO x 3ea,5 IO x 1ea)
▲Debug mode:Serial Wire Debug (SWD)
▲Timer/PWM
■1 Watchdog (32-bit down-counter)
■4 Timers (32-bit or 16-bit down-counter)
■8 PWMs (32-bit counter/timers with programmable 6-bit prescaler)
■1 RTC (calendar,alarm)
▲Communication Interfaces
■3 UART (2 UARTs with FIFO and Flow Control,1 simple UART)
■2 SPI
■2 I2C (Master/Slave,Fast-mode (400 kbps))
▲Crypto
■1 RNG (Random Number Generator):32-bit random number
▲Package:64 TQFP (7x7 mm)
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Datasheet |
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Please see the document for details |
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TQFP |
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English Chinese Chinese and English Japanese |
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2022/02/02 |
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436 KB |
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